1. Technical Field
The present disclosure relates generally to a constant false alarm rate (CFAR) device for a signal detection system and, more particularly, to a CFAR device that is capable of detecting a target signal in interference waves from a signal detection system, such as radar or sonar.
2. Description of the Related Art
Signal detection systems, such as radar or sonar, use a CFAR algorithm in order to detect a target signal from a signal including background noise, an interference signal, clutter, reverberations, etc.
That is, a CFAR algorithm is responsible for a function of detecting a target signal in radar or the like by comparing the sizes of an interference wave and a signal.
CFAR modules have details that vary depending on an applied CFAR algorithm. However, these CFAR modules calculate an interference wave based on adjacent frequency signals, compares the size of the calculated interference wave with that of a test signal, and detects the test signal as a target when the size of the test signal is larger than that of the interference wave by a predetermined value, in the same manner. The adjacent frequency signals become prior signals (adjacent frequency signals of lower frequencies) and posterior signals (adjacent frequency signals of higher frequencies) in connection with the frequency of the test signal.
The paper “A Versatile Hardware Architecture for a Constant False Alarm Rate Processor based on a Linear Insertion Sorter, Roberto Perez-Andrade et al., Digital Signal Processing 20 2010 1733-1747” discloses hardware in which the most widely used ordered statistics CFAR (OS-CFAR) and cell average CFAR (CA-CFAR) have been implemented together.
The structure of the CFAR hardware (also referred to as a “CFAR processor”) described in the paper is illustrated in FIG. 1. The CFAR processor of FIG. 1 includes two sorting basic cell (SBC) sorting arrays 1a and 1b for 2n reference cells, (2m+1) shift registers 2 for guard cells, and a cell under test (CUT) 3 located between the registers 2. In this case, the CUT 30 may be more appropriately referred to as a test signal cell, and a signal input to the test signal cell may be referred to as a test signal CUT. The CFAR processor of FIG. 1 includes two multiplexers 4a and 4b having n inputs and a single output that perform a rank operation for the lagging and leading sorting arrays.
In connection with CFAR, in interference wave evaluation, frequencies immediately adjacent to a signal under test are generally excluded. This exerts influence that increases the size of adjacent frequency signals when a signal is a target and the signal size level of this signal is high. For this reason, when the signal levels of immediately adjacent frequencies are used in interference wave analysis, the accuracy of the analysis is degraded. The adjacent frequency regions excluded from interference wave signal analysis as described above correspond to the guard cell parts of the shift registers 2 in FIG. 1.
Meanwhile, in the case where the structure of FIG. 1 is employed without change, when a guard cell size is changed, hardware design code must be modified, or recombination is required even when design has been performed using a guard cell number as a parameter (i.e., parameterized design has been performed).
As a related technology, Korean Patent No. 1040315 entitled “Target Detection Apparatus Adaptive to Clutter Environment” discloses a technology in which a determination criterion used to determine the presence of a target signal is dualized and the determination criterion is adaptively changed depending on a current clutter environment, thereby improving the performance of target signal detection.